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Preliminary Technical Data
ADSP-219x DSP CORE FEATURES 6.25 ns Instruction Cycle Time (Internal), for up to 160 MIPS Sustained Performance ADSP-218x Family Code Compatible with the Same Easy -to-Use Algebraic Syntax Single-Cycle Instruction Execution Up to 16M words of Addressable Memory Space with 24 Bits of Addressing Width Dual Purpose Program Memory for Both Instruction and Data Storage Fully Transparent Instruction Cache Allows Dual Operand Fetches in Every Instruction Cycle Unified Memory Space Permits Flexible Address Generation, Using Two Independent DAG Units
DSP Microcomputer ADSP-2196
Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units with Dual 40-bit Accumulators Single-Cycle Context Switch between Two Sets of Computational and DAG Registers Parallel Execution of Computation and Memory Instructions Pipelined Architecture Supports Efficient Code Execution at Speeds up to 160 MIPS Register File Computations with All Nonconditional, Nonparallel Computational Instructions Powerful Program Sequencer Provides Zero-Overhead Looping and Conditional Instruction Execution Architectural Enhancements for Compiled C Code Efficiency
FUNCTIONAL BLOCK DIAGRAM
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REV. PrA
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35(/,0,1$5< 7(&+1,&$/ '$7$ ADSP-2196
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September 2001
ADSP-2196 DSP FEATURES 16K Words of On-Chip RAM, Configured as 8K Words On-Chip 24-bit RAM and 8K Words On-Chip 16-bit RAM 16K Words of On-Chip 24-bit ROM Architecture Enhancements beyond ADSP-218x Family are Supported with Instruction Set Extensions for Added Registers, Ports, and Peripherals Flexible Power Management with Selectable Power-Down and Idle Modes Programmable PLL Supports 1 to 32 Frequency Multiplication, Enabling Full-Speed Operation from Low-Speed Input Clocks 2.5 V Internal Operation Supports 3.3 V Compliant I/O Three Full-Duplex Multichannel Serial Ports, Each Supporting H.100 Standard with A-Law and -Law Companding in Hardware Two SPI-Compatible Ports with DMA Capability One UART Port with DMA Capability 16 General-Purpose I/O Pins (Eight Dedicated/Eight Programmable from the External Memory Interface) with Integrated Interrupt Support Three Programmable 32-Bit Interval Timers with Pulsewidth Counter, PWM Generation, and Externally Clocked Timer Capabilities Up to 11 DMA Channels can be Active at any Given Time Host Port With DMA Capability for Efficient, Glueless Host Interface (16-Bit Transfers)
External Memory Interface Features Include: Direct Access from the DSP to External Memory for Data and Instructions. Support for DMA Block Transfers to/from External Memory. Separate Peripheral Memory Space with Parallel Support for 224K External 16-Bit Registers. Four General-Purpose Memory Select Signals that Provide Access to Separate Banks of External Memory. Bank Boundaries and Size Are UserProgrammable. Programmable Waitstate Logic with ACK Signal and Separate Read and Write Wait Counts. Wait Mode Completion Supports All Combinations of ACK and/or Wait Count. I/O Clock Rate Can Be Set to the Peripheral Clock Rate Divided by 1, 2, 4, 16, or 32 to Allow Interface to Slow Memory Devices. Address Translation and Data Word Packing is Provided to Support an 8- or 16-Bit External Data Bus. Programmable Read and Write Strobe Polarity. Separate Configuration Registers for the Four General-Purpose, Peripheral, and Boot Memory Spaces. Bus Request and Grant Signals Support the Use of the External Bus by an External Device. Boot Methods Include Booting Through External Memory Interface, SPI Ports, UART Port, or Host Interface IEEE JTAG Standard 1149.1 Test Access Port Supports On-Chip Emulation and System Debugging 144-Lead LQFP Package (20 20 1.4 mm) and 144-Lead Mini-BGA Package (10 10 1.25 mm)
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ADSP-2196
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TABLE OF CONTENTS ADSP-219x dSP Core Features . . . . . . . . . . . . . . . . . . . 1
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . 1 ADSP-2196 DSP Features . . . . . . . . . . . . . . . . . . . . . 2 General Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DSP Core Architecture . . . . . . . . . . . . . . . . . . . . 4 DSP Peripherals Architecture . . . . . . . . . . . . . . . 5 Memory Architecture . . . . . . . . . . . . . . . . . . . . . 6 Internal (On-Chip) Memory . . . . . . . . . . . . . . . . 6 Internal On-Chip ROM . . . . . . . . . . . . . . . . . . . . 6 On-Chip Memory Security . . . . . . . . . . . . . . . . . 7 External (Off-Chip) Memory . . . . . . . . . . . . . . . . 7 External Memory Space . . . . . . . . . . . . . . . . . . . . 7 I/O Memory Space . . . . . . . . . . . . . . . . . . . . . . . 7 Boot Memory Space . . . . . . . . . . . . . . . . . . . . . . 7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . 10 Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Host Port Acknowledge (HACK) Modes . . . . . . 10 Host Port Chip Selects . . . . . . . . . . . . . . . . . . . 11 DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . 11 Serial Peripheral Interface (SPI) Ports . . . . . . . . 12 UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Programmable Flag (PFx) Pins . . . . . . . . . . . . . 13 Low Power Operation . . . . . . . . . . . . . . . . . . . . 13 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-down Core Mode . . . . . . . . . . . . . . . . . . 13 Power-Down Core/Peripherals Mode . . . . . . . . . 13 Power-Down All Mode . . . . . . . . . . . . . . . . . . . 14 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . 15 Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Request and Bus Grant . . . . . . . . . . . . . . . . 16 Instruction Set Description . . . . . . . . . . . . . . . . 16 Development Tools . . . . . . . . . . . . . . . . . . . . . . 16 Designing an Emulator-Compatible DSP Board (Target) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Target Board Header . . . . . . . . . . . . . . . . . . . . . 17 JTAG Emulator Pod Connector . . . . . . . . . . . . 18 Design-for-Emulation Circuit Information . . . . . 18 Additional Information . . . . . . . . . . . . . . . . . . . 18 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . ABSOLUTE MAXIMUM RATINGS . . . . . . . ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . Clock In and Clock Out Cycle Timing . . . . . . . Programmable Flags Cycle Timing . . . . . . . . . . Timer PWM_OUT Cycle Timing . . . . . . . . . . . External Port Write Cycle Timing . . . . . . . . . . . External Port Read Cycle Timing . . . . . . . . . . . External Port Bus Request and Grant Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Port ALE Mode Write Cycle Timing . . . . Host Port ACC Mode Write Cycle Timing . . . . Host Port ALE Mode Read Cycle Timing . . . . . Host Port ACC Mode Read Cycle Timing . . . . Serial Port (SPORT) Clocks and Data Timing . Serial Port (SPORT) Frame Synch Timing . . . . Serial Peripheral Interface (SPI) Port--Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) Port--Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Asynchronous Receiver-Transmitter (UART) Port--Receive and Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Test And Emulation Port Timing . . . . . . Output Drive Currents . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . Output Disable Time . . . . . . . . . . . . . . . . . . . . Output Enable Time . . . . . . . . . . . . . . . . . . . . . Example System Hold Time Calculation . . . . . . Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . Environmental Conditions . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . ADSP-2196 144-Lead LQFP Pinout . . . . . . . . . ADSP-2196 144-Lead Mini-BGA Pinout . . . . . 144-Lead Metric Thin Plastic Quad Flatpack (LQFP) (ST-144) . . . . . . . . . . . . . . . . . . . 144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . .
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35(/,0,1$5< 7(&+1,&$/ '$7$ ADSP-2196
General Note
For current information contact Analog Devices at 800/262-5643
September 2001
This data sheet provides preliminary information for the ADSP-2196 Digital Signal Processor.
GENERAL DESCRIPTION
* Receive or transmit data over two SPI ports * Access external memory through the external memory interface * Decrement the timers
DSP Core Architecture
The ADSP-2196 DSP is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2196 combines the ADSP-219x family base architecture (three computational units, two data address generators, and a program sequencer) with three serial ports, two SPI-compatible ports, one UART port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces. The ADSP-2196 architecture is code-compatible with ADSP-218x family DSPs. Although the architectures are compatible, the ADSP-2196 architecture has a number of enhancements over the ADSP-218x architecture. The enhancements to computational units, data address generators, and program sequencer make the ADSP-2196 more flexible and even easier to program than the ADSP-218x DSPs. Indirect addressing options provide addressing flexibility-- premodify with no update, pre- and post-modify by an immediate 8-bit, two's-complement value and base address registers for easier implementation of circular buffering. The ADSP-2196 integrates 32K words of on-chip memory configured as 8K words (24-bit) of program RAM, 8K words (16-bit) of data RAM, and 16K words (24-bit) of program ROM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-2196 is available in 144-lead LQFP and mini-BGA packages. Fabricated in a high-speed, low-power, CMOS process, the ADSP-2196 operates with a 6.25 ns instruction cycle time (160 MIPS). All instructions, except two multiword instructions, can execute in a single DSP cycle. The ADSP-2196's flexible architecture and comprehensive instruction set support multiple operations in parallel. For example, in one processor cycle, the ADSP-2196 can: * * * * * Generate an address for the next instruction fetch Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computational operation
The ADSP-2196 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every single-word instruction can be executed in a single processor cycle. The ADSP-2196 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. The functional block diagram on page 1 shows the architecture of the ADSP-219x core. It contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data from the register file and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations. The MAC has two 40-bit accumulators, which help with overflow. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations. Register-usage rules influence placement of input and results within the computational units. For most operations, the computational units' data registers act as a data register file, permitting any input or result register to provide input to any unit for a computation. For feedback operations, the computational units let the output (result) of any unit be input to any unit on the next cycle. For conditional or multifunction instructions, there are restrictions on which data registers may provide inputs or receive results from each computational unit. For more information, see the ADSP-219x DSP Instruction Set Reference. A powerful program sequencer controls the flow of instruction execution. The sequencer supports conditional jumps, subroutine calls, and low interrupt overhead. With internal loop counters and loop stacks, the ADSP-2196 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four 16-bit address pointers. Whenever the pointer is used to access data (indirect addressing), it is pre- or post-modified by the value of one of four possible modify registers. A length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. Page registers in the DAGs allow circular addressing REV. PrA
These operations take place while the processor continues to: * Receive and transmit data through two serial ports * Receive and/or transmit data from a Host * Receive or transmit data through the UART
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
35(/,0,1$5< 7(&+1,&$/ '$7$ September 2001
For current information contact Analog Devices at 800/262-5643
ADSP-2196
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within 64K word boundaries of each of the 256 memory pages, but these buffers may not cross page boundaries. Secondary registers duplicate all the primary registers in the DAGs; switching between primary and secondary registers provides a fast context switch. Efficient data transfer in the core is achieved with the use of internal buses: * * * * * * Program Memory Address (PMA) Bus Program Memory Data (PMD) Bus Data Memory Address (DMA) Bus Data Memory Data (DMD) Bus DMA Address Bus DMA Data Bus
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The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Boot memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting the ADSP-2196 to fetch two operands in a single cycle, one from program memory and one from data memory. The DSP's dual memory buses also let the ADSP-219x core fetch an operand from data memory and the next instruction from program memory in a single cycle.
DSP Peripherals Architecture
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The functional block diagram on page 1 shows the DSP's on-chip peripherals, which include the external memory interface, Host port, serial ports, SPI-compatible ports, UART port, JTAG test and emulation port, timers, flags, and interrupt controller. These on-chip peripherals can connect to off-chip devices as shown in Figure 1. The ADSP-2196 has a 16-bit Host port with DMA capability that lets external Hosts access on-chip memory. This 24-pin parallel port consists of a 16-pin multiplexed data/address bus and provides a low-service overhead data move capability. Configurable for 8- or 16-bits, this port provides a glueless interface to a wide variety of 8- and 16-bit microcontrollers. Two chip-selects provide Hosts access to the DSP's entire memory map. The DSP is bootable through this port. The ADSP-2196 also has an external memory interface that is shared by the DSP's core, the DMA controller, and DMA capable peripherals, which include the UART, SPORT0, SPORT1, SPORT2, SPI0, SPI1, and the Host port. The external port consists of a 16-bit data bus, a 22-bit address bus, and control signals. The data bus is configurable to provide an 8 or 16 bit interface to external memory. Support for word packing lets the DSP access 16- or 24-bit words from external memory regardless of the external data bus width. When configured for an 8-bit interface, the unused
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Figure 1. ADSP-2196 System Diagram
eight lines provide eight programmable, bidirectional general-purpose Programmable Flag lines, six of which can be mapped to software condition signals. The memory DMA controller lets the ADSP-2196 move data and instructions from between memory spaces: internal-to-external, internal-to-internal, and external-toexternal. On-chip peripherals can also use this controller for DMA transfers. The ADSP-2196 can respond to up to seventeen interrupts at any given time: three internal (stack, emulator kernel, and power-down), two external (emulator and reset), and twelve user-defined (peripherals) interrupts. Programmers assign 5
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35(/,0,1$5< 7(&+1,&$/ '$7$ ADSP-2196
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September 2001
a peripheral to one of the 12 user-defined interrupts. These assignments determine the priority of each peripheral for interrupt service. There are three serial ports on the ADSP-2196 that provide a complete synchronous, full-duplex serial interface. This interface includes optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each serial port can transmit or receive an internal or external, programmable serial clock and frame syncs. Each serial port supports 128-channel Time Division Multiplexing. The ADSP-2196 provides up to sixteen general-purpose I/O pins, which are programmable as either inputs or outputs. Eight of these pins are dedicated general purpose Programmable Flag pins. The other eight of them are multifunctional pins, acting as general purpose I/O pins when the DSP connects to an 8-bit external data bus and acting as the upper eight data pins when the DSP connects to a 16-bit external data bus. These Programmable Flag pins can implement edge- or level-sensitive interrupts, some of which can be used to base the execution of conditional instructions. Three programmable interval timers generate periodic interrupts. Each timer can be independently set to operate in one of three modes: * Pulse Waveform Generation mode * Pulsewidth Count/Capture mode * External Event Watchdog mode Each timer has one bi-directional pin and four registers that implement its mode of operation: A 7-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulsewidth register. A single status register supports all three timers. A bit in the mode status register globally enables or disables all three timers, and a bit in each timer's configuration register enables or disables the corresponding timer independently of the others.
Memory Architecture
the remaining 254 pages are addressable off-chip. I/O memory pages differ from external memory pages in that I/O pages are 1K word long, and the external I/O pages have their own select pin (IOMS). Pages 0-31 of I/O memory space reside on-chip and contain the configuration registers for the peripherals. Both the ADSP-2196 and DMA-capable peripherals can access the DSP's entire memory map.
Internal (On-Chip) Memory
The ADSP-2196's unified program and data memory space consists of 16M locations that are accessible through two 24-bit address buses, the PMA and DMA buses. The DSP uses slightly different mechanisms to generate a 24-bit address for each bus. The DSP has three functions that support access to the full memory map. * The DAGs generate 24-bit addresses for data fetches from the entire DSP memory address range. Because DAG index (address) registers are 16 bits wide and hold the lower 16 bits of the address, each of the DAGs has its own 8-bit page register (DMPGx) to hold the most significant eight address bits. Before a DAG generates an address, the program must set the DAG's DMPGx register to the appropriate memory page. * The Program Sequencer generates the addresses for instruction fetches. For relative addressing instructions, the program sequencer bases addresses for relative jumps, calls, and loops on the 24-bit Program Counter (PC). In direct addressing instructions (two-word instructions), the instruction provides an immediate 24-bit address value. The PC allows linear addressing of the full 24-bit address range. * For indirect jumps and calls that use a 16-bit DAG address register for part of the branch address, the Program Sequencer relies on an 8-bit Indirect Jump page (IJPG) register to supply the most significant eight address bits. Before a cross page jump or call, the program must set the program sequencer's IJPG register to the appropriate memory page. The ADSP-2196 has 1K word of on-chip ROM that holds boot routines. If peripheral booting is selected, the DSP starts executing instructions from the on-chip boot ROM, which starts the boot process from the selected peripheral. For more information, see Booting Modes on page 15. The on-chip boot ROM is located on Page 255 in the DSP's memory space map.
Internal On-Chip ROM
The ADSP-2196 DSP provides 16K words of on-chip SRAM memory. This memory is divided into two 8K blocks located on memory Page 0 in the DSP's memory map. The DSP also provides 16K words of on-chip ROM. In addition to the internal and external memory space, the ADSP-2196 can address two additional and separate off-chip memory spaces: I/O space and boot space. As shown in Figure 2, the DSP's two internal memory blocks populate all of Page 0. The entire DSP memory map consists of 256 pages (Pages 0-255), and each page is 64K words long. External memory space consists of four memory banks (banks 0-3) and supports a wide variety of SRAM memory devices. Each bank is selectable using the memory select pins (MS3-0) and has configurable page boundaries, waitstates, and waitstate modes. The 1K word of on-chip boot-ROM populates the top of Page 255 while 6
The ADSP-2196 DSP features a 16K-word x 24-bit on-chip maskable ROM mapped into program memory space (Figure 3). Customers can arrange to have the ROM programmed with application-specific code.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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ADSP-2196
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Figure 2. ADSP-2196 Memory Map On-Chip Memory Security
The ADSP-2196 has a maskable option to protect the contents of on-chip memories from being accessed. When the ROM protection is set, the on-chip ROM space cannot be accessed by a hardware emulator.
External (Off-Chip) Memory
Each of the ADSP-2196's off-chip memory spaces has a separate control register, so applications can configure unique access parameters for each space. The access parameters include read and write wait counts, waitstate completion mode, I/O clock divide ratio, write hold time extension, strobe polarity, and data bus width. The core clock and peripheral clock ratios influence the external memory access strobe widths. For more information, see Clock Signals on page 14. The off-chip memory spaces are: * External memory space (MS3-0 pins) * I/O memory space (IOMS pin) * Boot memory space (BMS pin) All of these off-chip memory spaces are accessible through the External Port, which can be configured for 8-bit or 16-bit data widths.
External Memory Space
memory have Bank0 containing pages 1-63, Bank1 containing pages 64-127, Bank2 containing pages 128-191, and Bank3 containing Pages 192-254. The MS3-0 memory bank pins select Banks 3-0, respectively. The external memory interface decodes the 8 MSBs of the DSP program address to select one of the four banks. Both the ADSP-219x core and DMA-capable peripherals can access the DSP's external memory space.
I/O Memory Space
The ADSP-2196 supports an additional external memory called I/O memory space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports a total of 256K locations. The first 8K addresses are reserved for on-chip peripherals. The upper 248K addresses are available for external peripheral devices. The DSP's instruction set provides instructions for accessing I/O space. These instructions use an 18-bit address that is assembled from an 8-bit I/O page (IOPG) register and a 10-bit immediate value supplied in the instruction. Both the ADSP-219x core and a Host (through the Host Port Interface) can access I/O memory space.
Boot Memory Space
External memory space consists of four memory banks. These banks can contain a configurable number of 64K word pages. At reset, the page boundaries for external REV. PrA
Boot memory space consists of one off-chip bank with 254 pages. The BMS memory bank pin selects boot memory space. Both the ADSP-219x core and DMA-capable 7
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Figure 3. ADSP-2196 Memory Map, with On-Chip ROM
peripherals can access the DSP's off-chip boot memory space. After reset, the DSP always starts executing instructions from the on-chip boot ROM. Depending on the boot configuration, the boot ROM code can start booting the DSP from boot memory. For more information, see Booting Modes on page 15.
Interrupts
Table 1. Interrupt Priorities/Addresses (Continued) IMASK/ IRPTL Vector Address1
Interrupt
Emulation Kernel User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt
3 4 5 6 7 8 9 10 11 12
0x00 0060 0x00 0080 0x00 00A0 0x00 00C0 0x00 00E0 0x00 0100 0x00 0120 0x00 0140 0x00 0160 0x00 0180
The interrupt controller lets the DSP respond to 17 interrupts with minimum overhead. The controller implements an interrupt priority scheme as shown in Table 1. Applications can use the unassigned slots for software and peripheral interrupts.
Table 1. Interrupt Priorities/Addresses IMASK/ IRPTL Vector Address1
User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt
Interrupt
Emulator (NMI)-- Highest Priority Reset (NMI) Power-Down (NMI) Loop and PC Stack
NA 0 1 2
NA 0x00 0000 0x00 0020 0x00 0040
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Reset Priority
Table 1. Interrupt Priorities/Addresses (Continued) IMASK/ IRPTL Vector Address1
Table 2. Peripheral Interrupts and Priority at Reset
Interrupt
Interrupt
ID
User Assigned Interrupt User Assigned Interrupt User Assigned Interrupt-- Lowest Priority
1
13 14 15
0x00 01A0 0x00 01C0 0x00 01E0
Programmable Flag 0 (any PFx) Programmable Flag 1 (any PFx) Memory DMA port
12 13 14
11 11 11
These interrupt vectors start at address 0x10000 when the DSP is in "no-boot", run-form-external memory mode.
Table 2 shows the ID and priority at reset of each of the peripheral interrupts. To assign the peripheral interrupts a different priority, applications write the new priority to their corresponding control bits (determined by their ID) in the Interrupt Priority Control register. The peripheral interrupt's position in the IMASK and IRPTL register and its vector address depend on its priority level, as shown in Table 1. Because the IMASK and IRPTL registers are limited to 16 bits, any peripheral interrupts assigned a priority level of 11 are aliased to the lowest priority bit position (15) in these registers and share vector address 0x00 01E0.
Table 2. Peripheral Interrupts and Priority at Reset Reset Priority
Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The emulation, power-down, and reset interrupts are nonmaskable with the IMASK register, but software can use the DIS INT instruction to mask the power-down interrupt. The Interrupt Control (ICNTL) register controls interrupt nesting and enables or disables interrupts globally. The general-purpose Programmable Flag (PFx) pins can be configured as outputs, can implement software interrupts, and (as inputs) can implement hardware interrupts. Programmable Flag pin interrupts can be configured for level-sensitive, single edge-sensitive, or dual edgesensitive operation.
Table 3. Interrupt Control (ICNTL) Register Bits Bit Description
Interrupt
ID
Slave DMA/Host Port Interface SPORT0 Receive SPORT0 Transmit SPORT1 Receive SPORT1 Transmit SPORT2 Receive/SPI0 SPORT2 Transmit/SPI1 UART Receive UART Transmit Timer A Timer B Timer C
0 1 2 3 4 5 6 7 8 9 10 11
0 1 2 3 4 5 6 7 8 9 10 11 0-3 4 5 6 7 8-9 10 11 12-15 Reserved Interrupt Nesting Enable Global Interrupt Enable Reserved MAC-Biased Rounding Enable Reserved PC Stack Interrupt Enable Loop Stack Interrupt Enable Reserved
The IRPTL register is used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. To support interrupt, loop, and subroutine nesting, the PC stack is 33 levels deep, the loop stack is eight levels deep, and the status stack is 16 levels deep. To prevent stack overflow, the
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Arbitration Priority
PC stack can generate a stack-level interrupt if the PC stack falls below three locations full or rises above 28 locations full. The following instructions globally enable or disable interrupt servicing, regardless of the state of IMASK.
ENA INT; DIS INT;
Table 4. I/O Bus Arbitration Priority (Continued) DMA Bus Master
UART Receive DMA UART Transmit DMA Host Port DMA Memory DMA
Host Port
8 9 10 11--Lowest
At reset, interrupt servicing is disabled. For quick servicing of interrupts, a secondary set of DAG and computational registers exist. Switching between the primary and secondary registers lets programs quickly service interrupts, while preserving the DSP's state.
DMA Controller
The ADSP-2196 has a DMA controller that supports automated data transfers with minimal overhead for the DSP core. Cycle stealing DMA transfers can occur between the ADSP-2196's internal memory and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interface. DMA-capable peripherals include the Host port, SPORTs, SPI ports, and UART. Each individual DMA-capable peripheral has a dedicated DMA channel. To describe each DMA sequence, the DMA controller uses a set of parameters--called a DMA descriptor. When successive DMA sequences are needed, these DMA descriptors can be linked or chained together, so the completion of one DMA sequence auto-initiates and starts the next sequence. DMA sequences do not contend for bus access with the DSP core, instead DMAs "steal" cycles to access memory. All DMA transfers use the DMA bus shown in the functional block diagram on page 1. Because all of the peripherals use the same bus, arbitration for DMA bus access is needed. The arbitration for DMA bus access appears in Table 4.
Table 4. I/O Bus Arbitration Priority DMA Bus Master Arbitration Priority
The ADSP-2196's Host port functions as a slave on the external bus of an external Host. The Host port interface lets a Host read from or write to the DSP's memory space, boot space, or internal I/O space. Examples of Hosts include external microcontrollers, microprocessors, or ASICs. The Host port is a multiplexed address and data bus that provides both an 8-bit and a 16-bit data path and operates using an asynchronous transmission protocol. Through this port, an off-chip Host can directly access the DSP's entire memory space map, boot memory space, and internal I/O space. To access the DSP's internal memory space, a Host steals one cycle per access from the DSP. A Host access to the DSP's external memory uses the external port interface and does not stall (or steal cycles from) the DSP's core. Because a Host can access internal I/O memory space, a Host can control any of the DSP's I/O mapped peripherals. The Host port is most efficient when using the DSP as a slave and uses DMA to automate the incrementing of addresses for these accesses. In this case, an address does not have to be transferred from the Host for every data transfer.
Host Port Acknowledge (HACK) Modes
SPORT0 Receive DMA SPORT1 Receive DMA SPORT2 Receive DMA SPORT0 Transmit DMA SPORT1 Transmit DMA SPORT2 Transmit DMA SPI0 Receive/Transmit DMA SPI1 Receive/Transmit DMA
0--Highest 1 2 3 4 5 6 7
The Host port supports a number of modes (or protocols) for generating a HACK output for the host. The host selects ACK or Ready Modes using the HACK_P and HACK pins. The Host port also supports two modes for address control: Address Latch Enable (ALE) and Address Cycle Control (ACC) modes. The DSP auto-detects ALE versus ACC Mode from the HALE and HWR inputs. The host port HACK signal polarity is selected (only at reset) as active high or active low, depending on the value driven on the HACK_P pin.The HACK polarity is stored into the host port configuration register as a read only bit. The DSP uses HACK to indicate to the Host when to complete an access. For a read transaction, a Host can proceed and complete an access when valid data is present in the read buffer and the host port is not busy doing a write. For a write transactions, a Host can complete an access when the write buffer is not full and the host port is not busy doing a write.
10
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Two mode bits in the Host Port configuration register HPCR [7:6] define the functionality of the HACK line. HPCR6 is initialized at reset based on the values driven on HACK and HACK_P pins (shown in Table 5); HPCR7 is always cleared (0) at reset. HPCR [7:6] can be modified after reset by a write access to the host port configuration register.
Table 5. Host Port Acknowledge Mode Selection Values Driven At Reset HACK_P HACK HPCR [7:6] Initial Values Bit 7 Bit 6
a single DMA bus access to prefetch Host direct reads or to post direct writes. During assembly of larger words, the Host port interface asserts ACK for each byte access that does not start a read or complete a write. Otherwise, the Host port interface asserts ACK when it has completed the memory access successfully.
DSP Serial Ports (SPORTs)
Acknowledge Mode
The ADSP-2196 incorporates three complete synchronous serial ports (SPORT0, SPORT1, and SPORT2) for serial and multiprocessor communications. The SPORTs support the following features: * Bidirectional operation--each SPORT has independent transmit and receive pins. * Buffered (8-deep) transmit and receive ports--each port has a data register for transferring data words to and from other DSP components and shift registers for shifting data in and out of the data registers. * Clocking--each transmit and receive port can either use an external serial clock (75 MHz) or generate its own, in frequencies ranging from 1144 Hz to 75 MHz. * Word length--each SPORT supports serial data words from 3 to 16 bits in length transferred in Big Endian (MSB) or Little Endian (LSB) format. * Framing--each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulsewidths and early or late frame sync. * Companding in hardware--each SPORT can perform A-law or -law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. * DMA operations with single-cycle overhead--each SPORT can automatically receive and transmit multiple buffers of memory data, one data word each DSP cycle. Either the DSP's core or a Host processor can link or chain sequences of DMA transfers between a SPORT and memory. The chained DMA can be dynamically allocated and updated through the DMA descriptors (DMA transfer parameters) that set up the chain. * Interrupts--each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA. * Multichannel capability--each SPORT supports the H.100 standard.
0 0 1 1
0 1 0 1
0 0 0 0
1 0 0 1
Ready Mode ACK Mode ACK Mode Ready Mode
The functional modes selected by HPCR [7:6] are as follows (assuming active high signal): * ACK Mode--Acknowledge is active on strobes; HACK goes high from the leading edge of the strobe to indicate when the access can complete. After the Host samples the HACK active, it can complete the access by removing the strobe.The host port then removes the HACK. * Ready Mode--Ready active on strobes, goes low to insert wait state during the access.If the host port can not complete the access, it de-asserts the HACK/READY line. In this case, the Host has to extend the access by keeping the strobe asserted. When the Host samples the HACK asserted, it can then proceed and complete the access by de-asserting the strobe. While in Address Cycle Control (ACC) mode and the ACK or Ready acknowledge modes, the HACK is returned active for any address cycle.
Host Port Chip Selects
There are two chip-select signals associated with the Host Port: HCMS and HCIOMS. The Host Chip Memory Select (HCMS) lets the Host select the DSP and directly access the DSP's internal/external memory space or boot memory space. The Host Chip I/O Memory Select (HCIOMS) lets the Host select the DSP and directly access the DSP's internal I/O memory space. Before starting a direct access, the Host configures Host port interface registers, specifying the width of external data bus (8- or 16-bit) and the target address page (in the IJPG register). The DSP generates the needed memory select signals during the access, based on the target address. The Host port interface combines the data from one, two, or three consecutive Host accesses (up to one 24-bit value) into REV. PrA
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Serial Peripheral Interface (SPI) Ports
The DSP has two SPI-compatible ports that enable the DSP to communicate with multiple SPI-compatible devices. These ports are multiplexed with SPORT2, so either SPORT2 or the SPI ports are active, depending on the state of the OPMODE pin during hardware reset. The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSIx, and Master Input-Slave Output, MISOx) and a clock pin (Serial Clock, SCKx). Two SPI chip select input pins (SPISSx) let other SPI devices select the DSP, and fourteen SPI chip select output pins (SPIxSEL7-1) let the DSP select other SPI devices. The SPI select pins are reconfigured Programmable Flag pins. Using these pins, the SPI ports provide a full duplex, synchronous serial interface, which supports both master and slave modes and multimaster environments. Each SPI port's baud rate and clock phase/polarities are programmable (see Figure 4), and each has an integrated DMA controller, configurable to support both transmit and receive data streams. The SPI's DMA controller can only service unidirectional accesses at any given time.
HCLK SPI Clock Rate = -------------------------------------2 x SPIBAUD Figure 4. SPI Clock Rate Calculation
In slave mode, the DSP's core performs the following sequence to set up the SPI port to receive data from a master transmitter: 1. Enables and configures the SPI slave port to match the operation parameters set up on the master (data size and transfer format) SPI transmitter. 2. Defines and generates a receive DMA descriptor in Page 0 of memory space to interrupt at the end of the data transfer (optional in DMA mode only). 3. Enables the SPI DMA engine for a receive access (optional in DMA mode only). 4. Starts receiving the data on the appropriate SPI SCKx edges after receiving an SPI chip select on an SPISSx input pin (reconfigured Programmable Flag pin) from a master In DMA mode only, reception continues until the SPI DMA word count transitions from 1 to 0. The DSP's core could continue, by queuing up the next DMA descriptor. A slave mode transmit operation is similar, except the DSP's core specifies the data buffer in memory space from which to transmit data, generates and relinquishes control of the transmit DMA descriptor, and begins filling the SPI port's data buffer. If the SPI controller isn't ready on time to transmit, it can transmit a "zero" word.
UART Port
During transfers, the SPI ports simultaneously transmit and receive by serially shifting data in and out on their two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines. In master mode, the DSP's core performs the following sequence to set up and initiate SPI transfers: 1. Enables and configures the SPI port's operation (data size, and transfer format). 2. Selects the target SPI slave with an SPIxSELy output pin (reconfigured Programmable Flag pin). 3. Defines one or more DMA descriptors in Page 0 of I/O memory space (optional in DMA mode only). 4. Enables the SPI DMA engine and specifies transfer direction (optional in DMA mode only). 5. In non-DMA mode only, reads or writes the SPI port receive or transmit data buffer. The SCKx line generates the programmed clock pulses for simultaneously shifting data out on MOSIx and shifting data in on MISOx. In DMA mode only, transfers continue until the SPI DMA word count transitions from 1 to 0.
The UART port provides a simplified UART interface to another peripheral or Host. It performs full duplex, asynchronous transfers of serial data. Options for the UART include support for 5-8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The UART port supports two modes of operation: * PIO (programmed I/O) The DSP's core sends or receives data by writing or reading I/O-mapped UATX or UARX registers, respectively. The data is double-buffered on both transmit and receive. * DMA (direct memory access) The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels. These DMA channels have lower priority than most DMA channels because of their relatively low service rates. The UART's baud rate (see Figure 5), serial data format, error code generation and status, and interrupts are programmable: * Supported bit rates range from 95 bits to 6.25M bits per second (100 MHz peripheral clock). * Supported data formats are 7- or 12-bit frames. * Transmit and receive status can be configured to generate maskable interrupts to the DSP's core. REV. PrA
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HCLK UART Clock Rate = -----------------16 x D Figure 5. UART Clock Rate Calculation1
1
Low Power Operation
Where D = 1 to 65536
The timers can be used to provide a hardware-assisted autobaud detection mechanism for the UART interface.
Programmable Flag (PFx) Pins
The ADSP-2196 has 16 bidirectional, general-purpose I/O, Programmable Flag (PF15-0) pins. The PF7-0 pins are dedicated to general-purpose I/O. The PF15-8 pins serve either as general-purpose I/O pins (if the DSP is connected to an 8-bit external data bus) or serve as DATA15-8 lines (if the DSP is connected to a 16-bit external data bus). The Programmable Flag pins have special functions for clock multiplier selection and for SPI port operation. For more information, see Serial Peripheral Interface (SPI) Ports on page 12 and Clock Signals on page 14. Ten memory-mapped registers control operation of the Programmable Flag pins: * Flag Direction register Specifies the direction of each individual PFx pin as input or output. * Flag Control and Status registers Specify the value to drive on each individual PFx output pin. As input, software can predicate instruction execution on the value of individual PFx input pins captured in this register. One register sets bits, and one register clears bits. * Flag Interrupt Mask registers Enable and disable each individual PFx pin to function as an interrupt to the DSP's core. One register sets bits to enable interrupt function, and one register clears bits to disable interrupt function. Input PFx pins function as hardware interrupts, and output PFx pins function as software interrupts--latching in the IMASK and IRPTL registers. * Flag Interrupt Polarity register Specifies the polarity (active high or low) for interrupt sensitivity on each individual PFx pin. * Flag Sensitivity registers Specify whether individual PFx pins are level- or edge-sensitive and specify--if edge-sensitive--whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity.
The ADSP-2196 has four low-power options that significantly reduce the power dissipation when the device operates under standby conditions. To enter any of these modes, the DSP executes an IDLE instruction. The ADSP-2196 uses configuration of the PDWN, STOPCK, and STOPALL bits in the PLLCTL register to select between the low-power modes as the DSP executes the IDLE. Depending on the mode, an IDLE shuts off clocks to different parts of the DSP in the different modes. The low power modes are: * * * * Idle Power-Down Core Power-Down Core/Peripherals Power-Down All
Idle Mode
When the ADSP-2196 is in Idle mode, the DSP core stops executing instructions, retains the contents of the instruction pipeline, and waits for an interrupt. The core clock and peripheral clock continue running. To enter Idle mode, the DSP can execute the IDLE instruction anywhere in code. To exit Idle mode, the DSP responds to an interrupt and (after two cycles of latency) resumes executing instructions with the instruction after the IDLE.
Power-down Core Mode
When the ADSP-2196 is in Power-Down Core mode, the DSP core clock is off, but the DSP retains the contents of the pipeline and keeps the PLL running. The peripheral bus keeps running, letting the peripherals receive data. To enter Power-Down Core mode, the DSP executes an IDLE instruction after performing the following tasks: * * * * * Enter a power-down interrupt service routine Check for pending interrupts and I/O service routines Clear (= 0) the PDWN bit in the PLLCTL register Clear (= 0) the STOPALL bit in the PLLCTL register Set (= 1) the STOPCK bit in the PLLCTL register
To exit Power-Down Core mode, the DSP responds to an interrupt and (after two cycles of latency) resumes executing instructions with the instruction after the IDLE.
Power-Down Core/Peripherals Mode
When the ADSP-2196 is in Power-Down Core/Peripherals mode, the DSP core clock and peripheral bus clock are off, but the DSP keeps the PLL running. The DSP does not retain the contents of the instruction pipeline.The peripheral bus is stopped, so the peripherals cannot receive data. To enter Power-Down Core/Peripherals mode, the DSP executes an IDLE instruction after performing the following tasks: * Enter a power-down interrupt service routine * Check for pending interrupts and I/O service routines
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* Clear (= 0) the PDWN bit in the PLLCTL register * Set (= 1) the STOPALL bit in the PLLCTL register To exit Power-Down Core/Peripherals mode, the DSP responds to an interrupt and (after five to six cycles of latency) resumes executing instructions with the instruction after the IDLE.
Power-Down All Mode
All on-chip peripherals for the ADSP-2196 operate at the rate set by the peripheral clock. The peripheral clock is either equal to the core clock rate or one-half the DSP core clock rate. This selection is controlled by the IOSEL bit in the PLLCTL register. The maximum core clock is 160 MHz, and the maximum peripheral clock is 100 MHz--the combination of the input clock and core/peripheral clock ratios may not exceed these limits.
When the ADSP-2196 is in Power-Down All mode, the DSP core clock, the peripheral clock, and the PLL are all stopped. The DSP does not retain the contents of the instruction pipeline. The peripheral bus is stopped, so the peripherals cannot receive data. To enter Power-Down All mode, the DSP executes an IDLE instruction after performing the following tasks: * Enter a power-down interrupt service routine * Check for pending interrupts and I/O service routines * Set (= 1) the PDWN bit in the PLLCTL register To exit Power-Down Core/Peripherals mode, the DSP responds to an interrupt and (after 500 cycles to re-stabilize the PLL) resumes executing instructions with the instruction after the IDLE.
Clock Signals
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The ADSP-2196 can be clocked by a crystal oscillator or a buffered, shaped clock derived from an external clock oscillator. If a crystal oscillator is used, the crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 6. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used for this configuration. If a buffered, shaped clock is used, this external clock connects to the DSP's CLKIN pin. CLKIN input cannot be halted, changed, or operated below the specified frequency during normal operation. This clock signal should be a TTL-compatible signal. When an external clock is used, the XTAL input must be left unconnected. The DSP provides a user-programmable 1 to 32 multiplication of the input clock, including some fractional values, to support 128 external to internal (DSP core) clock ratios. The MSEL6-0, BYPASS, and DF pins decide the PLL multiplication factor at reset. At runtime, the multiplication factor can be controlled in software. To support input clocks greater that 100 MHz, the PLL uses an additional input: the Divide Frequency (DF) pin. If the input clock is greater than 100 MHz, DF must be high. If the input clock is less than 100 MHz, DF must be low. The combination of pullup and pull-down resistors in Figure 6 set up a core clock ratio of 6:1, which produces a 150 MHz core clock from the 25 MHz input. For other clock multiplier settings, see the ADSP-219x/2191 DSP Hardware Reference. The peripheral clock is supplied to the CLKOUT pin. 14
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Figure 6. External Crystal Connections Reset
The RESET signal initiates a master reset of the ADSP-2196. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power up, the clock does not continue to run and requires stabilization time when recovering from reset. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 100 s ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During
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this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, tRSP. The RESET input contains some hysteresis. If using an RC circuit to generate your RESET signal, the circuit should use an external Schmidt trigger. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and resets all registers to their default values (where applicable). When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. Program control jumps to the location of the on-chip boot ROM (0xFF0000).
Power Supplies
The OPMODE, BMODE1, and BMODE0 pins, sampled during hardware reset, and three bits in the Reset Configuration Register implement these modes: * Boot from memory external 16 bits--The memory boot routine located in boot ROM memory space executes a boot-stream-formatted program located at address 0x10000 of boot memory space, packing 16-bit external data into 24-bit internal data. The External Port Interface is configured for the default clock multiplier (128) and read waitstates (7). * Boot from EPROM--The EPROM boot routine located in boot ROM memory space executes a boot-stream-formatted program located at address 0x10000 of boot memory space, packing 8- or 16-bit external data into 24-bit internal data. The External Port Interface is configured for the default clock multiplier (32) and read waitstates (7). * Boot from Host--The (8- or 16-bit) Host downloads a boot-stream-formatted program to internal or external memory. The Host's boot routine is located in internal ROM memory space and uses the top 16 locations of Page 0 program memory and the top 272 locations of Page 0 data memory. The internal boot ROM sets semaphore A (an IO register within the host port) and then polls until the semaphore is reset. Once detected, the internal boot ROM will remap the interrupt vector table to Page 0 internal memory and jump to address 0x0000 internal. From the point of view of the host interface, an external host has full control of the DSP's memory map. The Host has the freedom to directly write internal memory, external memory, and internal I/O memory space. The DSP core execution is held off until the Host clears the semaphore register. This strategy allows the maximum flexibility for the Host to boot in the program and data code, by leaving it up to the programmer. * Execute from memory external 8 bits (No Boot)-- execution starts from Page 1 of external memory space, packing either 8- or 16-bit external data into 24-bit internal data. The External Port Interface is configured for the default clock multiplier (128) and read waitstates (7). * Boot from UART--The Host downloads boot-stream-formatted program using an autobaud handshake sequence. The Host agent selects a baud rate within the UART's clocking capabilities. After a hardware reset, the DSP's UART transmits 0xFF values (eight bits data, one start bit, one stop bit, no parity bit) until detecting the start of the first memory block. The UART boot routine is located in internal ROM memory space and uses the top 16 locations of Page 0 program memory and the top 272 locations of Page 0 data memory.
The ADSP-2196 has separate power supply connections for the internal (VDDINT) and external (VDDEXT) power supplies. The internal supply must meet the 2.5 V requirement. The external supply must be connected to a 3.3 V supply. All external supply pins must be connected to the same supply. As indicated in Table 6, the OPMODE pin has a dual role, acting as a boot mode select during reset and determining SPORT or SPI operation at runtime. If the OPMODE pin at reset is the opposite of what is needed in an application during runtime, the application needs to set the OPMODE bit appropriately during runtime prior to using the corresponding peripheral.
Booting Modes
The ADSP-2196 has seven mechanisms (listed in Table 6) for automatically loading internal program memory after reset.
Table 6. Select Boot Mode (OPMODE, BMODE1, and BMODE0) OPMODE BMODE1 BMODE0
Function
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Execute from external memory 16 bits (No Boot) Boot from EPROM Boot from Host Reserved Execute from external memory 8 bits (No Boot) Boot from UART Boot from SPI, up to 4K bits Boot from SPI, >4K bits up to 512K bits
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* Boot from SPI, up to 4K bits--The SPI0 port uses the SPI0SEL1 (reconfigured PF2) output pin to select a single serial EPROM device, submits a read command at address 0x00, and begins clocking consecutive data into internal or external memory. Use only SPI-compatible EPROMs of 4K bit (12-bit address range). The SPI0 boot routine located in internal ROM memory space executes a boot-stream-formatted program, using the top 16 locations of Page 0 program memory and the top 272 locations of Page 0 data memory. The SPI boot configuration is SPIBAUD0=60 (decimal), CPHA=1, CPOL=1, 8-bit data, and MSB first. * Boot from SPI, from >4K bits to 512K bits--The SPI0 port uses the SPI0SEL1 (re-configured PF2) output pin to select a single serial EPROM device, submits a read command at address 0x00, and begins clocking consecutive data into internal or external memory. Use only SPI-compatible EPROMs of 4K bit (16-bit address range). The SPI0 boot routine located in internal ROM memory space executes a boot-stream-formatted program, using the top 16 locations of Page 0 program memory and the top 272 locations of Page 0 data memory.
Bus Request and Bus Grant
The ADSP-2196 asserts the BGH pin when it is ready to start another external port access, but is held off because the bus was previously granted. This mechanism can be extended to define more complex arbitration protocols for implementing more elaborate multimaster systems.
Instruction Set Description
The ADSP-2196 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor's unique architecture, offers the following benefits: * ADSP-219x assembly language syntax is a superset of and source-code-compatible (except for two data registers and DAG base address registers) with ADSP-218x family syntax. It may be necessary to restructure ADSP-218x programs to accommodate the ADSP-2196's unified memory space and to conform to its interrupt vector map. * The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation. * Every instruction, but two, assembles into a single, 24-bit word that can execute in a single instruction cycle. The exceptions are two dual word instructions. One writes 16or 24-bit immediate data to memory, and the other is an absolute jump/call with the 24-bit address specified in the instruction. * Multifunction instructions allow parallel execution of an arithmetic, MAC, or shift instruction with up to two fetches or one write to processor memory space during a single instruction cycle. * Program flow instructions support a wider variety of conditional and unconditional jumps/calls and a larger set of conditions on which to base execution of conditional instructions.
Development Tools
The ADSP-2196 can relinquish control of the data and address buses to an external device. When the external device requires access to the bus, it asserts the bus request (BR) signal. The (BR) signal is arbitrated with core and peripheral requests. External Bus requests have the lowest priority. If no other internal request is pending, the external bus request will be granted. Due to synchronizer and arbitration delays, bus grants will be provided with a minimum of three peripheral clock delays. The ADSP-2196 will respond to the bus grant by: * Three-stating the data and address buses and the MS3-0, BMS, IOMS, RD, and WR output drivers. * Asserting the bus grant (BG) signal. The ADSP-2196 will halt program execution if the bus is granted to an external device and an instruction fetch or data read/write request is made to external general-purpose or peripheral memory spaces. If an instruction requires two external memory read accesses, the bus will not be granted between the two accesses. If an instruction requires an external memory read and an external memory write access, the bus may be granted between the two accesses. The external memory interface can be configured so that the core will have exclusive use of the interface. DMA and Bus Requests will be granted. When the external device releases BR, the DSP releases BG and continues program execution from the point at which it stopped. The bus request feature operates at all times, even while the DSP is booting and RESET is active.
The ADSP-2196 is supported with a complete set of software and hardware development tools, including Analog Devices' emulators and VisualDSP++(R) development environment. The same emulator hardware that supports other ADSP-219x DSPs, also fully emulates the ADSP-2196. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simula-
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tor, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. Two key points for these tools are: * Compiled ADSP-219x C/C++ code efficiency--the compiler has been developed for efficient translation of C/C++ code to ADSP-219x assembly. The DSP has architectural features that improve the efficiency of compiled C/C++ code. * ADSP-218x family code compatibility--The assembler has legacy features to ease the conversion of existing ADSP-218x applications to the ADSP-219x. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: * View mixed C/C++ and assembly code (interleaved source and object information) * Insert break points * Set conditional breakpoints on registers, memory, and stacks * Trace instruction execution * Perform linear or statistical profiling of program execution * Fill, dump, and graphically plot the contents of memory * Source level debugging * Create custom debugger windows The VisualDSP++ IDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the ADSP-219x development tools, including the syntax highlighting in the VisualDSP++ editor. This capability permits: * Control how the development tools process inputs and generate outputs. * Maintain a one-to-one correspondence with the tool's command line switches. Analog Devices' DSP emulators use the IEEE 1149.1 JTAG test access port of the ADSP-2196 processor to monitor and control the target board processor during emulation. The emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor's JTAG interface--the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the ADSP-219x processor family. Hardware tools include ADSP-219x PC plug-in cards. Third Party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
Designing an Emulator-Compatible DSP Board (Target)
The White Mountain DSP (Product Line of Analog Devices, Inc.) family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target's design must include the interface between an Analog Devices' JTAG DSP and the emulation header on a custom DSP target board.
Target Board Header
The emulator interface to an Analog Devices' JTAG DSP is a 14-pin header, as shown in Figure 7. The customer must supply this header on the target board in order to communicate with the emulator. The interface consists of a standard dual row 0.025" square post header, set on 0.1" 0.1" spacing, with a minimum post length of 0.235". Pin 3 is the key position used to prevent the pod from being inserted backwards. This pin must be clipped on the target board. Also, the clearance (length, width, and height) around the header must be considered. Leave a clearance of at least 0.15" and 0.10" around the length and width of the header, and reserve a height clearance to attach and detach the pod connector.
* 1' . ( < 1 2 3 ,1 % 70 6 % 7& . % 75 6 7 % 7' , * 1'
(08
* 1' 70 6 7 &. 7 56 7 7 ', 7 '2
72 3 9,(:
Figure 7. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place)
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As can be seen in Figure 7, there are two sets of signals on the header. There are the standard JTAG signals TMS, TCK, TDI, TDO, TRST, and EMU used for emulation purposes (via an emulator). There are also secondary JTAG signals BTMS, BTCK, BTDI, and BTRST that are optionally used for board-level (boundary scan) testing. When the emulator is not connected to this header, place jumpers across BTMS, BTCK, BTRST, and BTDI as shown in Figure 8. This holds the JTAG signals in the correct state to allow the DSP to run free. Remove all the jumpers when connecting the emulator to the JTAG header.
Figure 10. JTAG Pod Connector Keep-Out Area Design-for-Emulation Circuit Information
* 1'
(08
. ( < 1 2 3 ,1 % 70 6 % 7& . % 7' ,
* 1'
70 6 7 &.
For details on target board design issues including: single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)--use site search on "EE-68". This document is updated regularly to keep pace with improvements to emulator support.
Additional Information
% 75 6 7
7 56 7
7 ',
This data sheet provides a general overview of the ADSP-2196 architecture and functionality. For detailed information on the ADSP-219x family core architecture and instruction set, refer to the ADSP-219x/2191 DSP Hardware Reference.
PIN DESCRIPTIONS
* 1'
7 '2
72 3 9,(:
ADSP-2196 pin definitions are listed in Table 7. All ADSP-2196 inputs are asynchronous and can be asserted asynchronously to CLKIN (or to TCK for TRST). Unused inputs should be tied or pulled to VDDEXT or GND, except for ADDR21-0, DATA15-0, PF7-0, and inputs that have internal pull-up or pull-down resistors (TRST, BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, and RESET)--these pins can be left floating. These pins have a logic-level hold circuit that prevents input from floating internally. The following symbols appear in the Type column of Table 7: G = Ground, I = Input, O = Output, P = Power Supply, and T = Three-State.
Figure 8. JTAG Target Board Connector with No Local Boundary Scan JTAG Emulator Pod Connector
Figure 9 details the dimensions of the JTAG pod connector at the 14-pin target end. Figure 10 displays the keep-out area for a target board header. The keep-out area allows the pod connector to properly seat onto the target board header. This board area should contain no components (chips, resistors, capacitors, etc.). The dimensions are referenced to the center of the 0.25" square post pin.

Figure 9. JTAG Pod Connector Dimensions
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Table 7. Pin Descriptions Pin Type Function
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ADSP-2196
A21-0 D7-0 D15 /PF15 /SPI1SEL7 D14 /PF14 /SPI0SEL7 D13 /PF12 /SPI1SEL6 D12 /PF12 /SPI0SEL6 D11 /PF11 /SPI1SEL5 D10 /PF10 /SPI0SEL5 D9 /PF9 /SPI1SEL4 D8 /PF8 /SPI0SEL4 PF7 /SPI1SEL3 /DF PF6 /SPI0SEL3 /MSEL6 PF5 /SPI1SEL2 /MSEL5 PF4 /SPI0SEL2 /MSEL4 PF3 /SPI1SEL1 /MSEL3
O/T I/O/T I/O/T I/O I I/O/T I/O I I/O/T I/O I I/O/T I/O I I/O/T I/O I I/O/T I/O I I/O/T I/O I I/O/T I/O I I/O/T I I I/O/T I I I/O/T I I I/O/T I I I/O/T I I
External Port Address Bus External Port Data Bus, least significant 8 bits Data 15 (if 16-bit external bus)/Programmable Flags 15 (if 8-bit external bus)/SPI1 Slave Select output 7 (if 8-bit external bus, when SPI1 enabled) Data 14 (if 16-bit external bus)/Programmable Flags 14 (if 8-bit external bus)/SPI0 Slave Select output 7 (if 8-bit external bus, when SPI0 enabled) Data 13 (if 16-bit external bus)/Programmable Flags 13 (if 8-bit external bus)/SPI1 Slave Select output 6 (if 8-bit external bus, when SPI1 enabled) Data 12 (if 16-bit external bus)/Programmable Flags 12 (if 8-bit external bus)/SPI0 Slave Select output 6 (if 8-bit external bus, when SPI0 enabled) Data 11 (if 16-bit external bus)/Programmable Flags 11 (if 8-bit external bus)/SPI1 Slave Select output 5 (if 8-bit external bus, when SPI1 enabled) Data 10 (if 16-bit external bus)/Programmable Flags 10 (if 8-bit external bus)/SPI0 Slave Select output 5 (if 8-bit external bus, when SPI0 enabled) Data 9 (if 16-bit external bus)/Programmable Flags 9 (if 8-bit external bus)/SPI1 Slave Select output 4 (if 8-bit external bus, when SPI1 enabled) Data 8 (if 16-bit external bus)/Programmable Flags 8 (if 8-bit external bus)/SPI0 Slave Select output 4 (if 8-bit external bus, when SPI0 enabled) Programmable Flags 7/SPI1 Slave Select output 3 (when SPI0 enabled)/Divisor Frequency (divisor select for PLL input during boot) Programmable Flags 6/SPI0 Slave Select output 3 (when SPI0 enabled)/Multiplier Select 6 (during boot) Programmable Flags 5/SPI1 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 5 (during boot) Programmable Flags 4/SPI0 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 4 (during boot) Programmable Flags 3/SPI1 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 3 (during boot)
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Pin Type
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Table 7. Pin Descriptions (Continued) Function
PF2 /SPI0SEL1 /MSEL2 PF1 /SPISS1 /MSEL1 PF0 /SPISS0 /MSEL0 RD WR ACK BMS IOMS MS3-0 BR BG BGH HAD15-0 HA16 HACK_P HRD HWR HACK HALE HCMS HCIOMS CLKIN XTAL BMODE1-0 OPMODE CLKOUT BYPASS
I/O/T I I I/O/T I I I/O/T I I O/T O/T I O/T O/T O/T I O O I/O/T I I I I O I I I I O I I O I
Programmable Flags 2/SPI0 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 2 (during boot) Programmable Flags 1/SPI1 Slave Select input (when SPI1 enabled)/Multiplier Select 1 (during boot) Programmable Flags 0/SPI0 Slave Select input (when SPI0 enabled)/Multiplier Select 0 (during boot) External Port Read Strobe External Port Write Strobe External Port Access Ready Acknowledge External Port Boot Space Select External Port IO Space Select External Port Memory Space Selects External Port Bus Request External Port Bus Grant External Port Bus Grant Hang Host Port Multiplexed Address and Data Bus Host Port MSB of Address Bus Host Port ACK Polarity Host Port Read Strobe Host Port Write Strobe Host Port Access Ready Acknowledge Host Port Address Latch Strobe or Address Cycle Control Host Port Internal Memory-Internal I/O Memory-Boot Memory Select Host Port Internal I/O Memory Select Clock Input/Oscillator input Oscillator output Boot Mode 1-0. The BMODE1 and BMODE0 pins have 85 k internal pull-up resistors. Operating Mode. The OPMODE pin has a 85 k internal pull-up resistor. Clock Output Phase-Lock-Loop (PLL) Bypass mode. The BYPASS pin has a 85 k internal pull-up resistor. REV. PrA
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Pin Type
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Table 7. Pin Descriptions (Continued) Function
RCLK1-0 RCLK2/SCK1 RFS1-0 RFS2/MOSI1 TCLK1-0 TCLK2/SCK0 TFS1-0 TFS2/MOSI0 DR1-0 DR2/MISO1 DT1-0 DT2/MISO0 TMR2-0 RXD TXD RESET
I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/T I/O/T O/T I/O/T I/O/T I O I
SPORT1-0 Receive Clock SPORT2 Receive Clock/SPI1 Serial Clock SPORT1-0 Receive Frame Sync SPORT2 Receive Frame Sync/SPI1 Master-Output, Slave-Input data SPORT1-0 Transmit Clock SPORT2 Transmit Clock/SPI0 Serial Clock SPORT1-0 Transmit Frame Sync SPORT2 Transmit Frame Sync/SPI0 Master-Output, Slave-Input data SPORT1-0 Serial Data Receive SPORT2 Serial Data Receive/SPI1 Master-Input, Slave-Output data SPORT1-0 Serial Data Transmit SPORT2 Serial Data Transmit/SPI0 Master-Input, Slave-Output data Timer output or capture UART Serial Receive Data UART Serial Transmit Data Processor Reset. Resets the ADSP-2196 to a known state and begins execution at the program memory location specified by the hardware reset vector address. The RESET input must be asserted (low) at power-up. The RESET pin has a 85 k internal pull-up resistor. Test Clock (JTAG). Provides a clock for JTAG boundary scan. The TCK pin has a 85 k internal pull-up resistor. Test Mode Select (JTAG). Used to control the test state machine. The TMS pin has a 85 k internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic. The TDI pin has a 85 k internal pull-up resistor. Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-2196. The TRST pin has a 65 k internal pull-down resistor. Emulation Status (JTAG). Must be connected to the ADSP-2196 emulator target board connector only. Core Power Supply. Nominally 2.5 V dc and supplies the DSP's core processor. (four pins). I/O Power Supply; Nominally 3.3 V dc. (nine pins). Power Supply Return. (twelve pins). Do Not Connect. Reserved pins that must be left open and unconnected.
TCK TMS TDI TDO TRST
I I I O I
EMU VDDINT VDDEXT GND NC REV. PrA
O P P G
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RECOMMENDED OPERATING CONDITIONS
Parameter Description1 Min Max Unit
VDDINT VDDEXT VIH1 VIH2 VIL TAMB
1 2
Internal (Core) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage2, @ VDDINT = max High Level Input Voltage3, @ VDDINT = max Low Level Input Voltage2, @ VDDINT = min Ambient Operating Temperature
2.37 TBD 2.0 2.2 -0.3 0
2.63 3.6 VDDEXT VDDEXT 0.6 70
V V V V V C
Specifications subject to change without notice. Applies to input and bidirectional pins: DATA15-0, HAD15-0, HA16, HALE, HACK, HACK_P, BYPASS, HRD, HWR, ACK, PF7-0, HCMS, HCIOMS, BR, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1, RFS2/MOSI1, OPMODE, BMODE1-0, TMS, TDI, TCK, DT2/MISO0, DR0, DR1, DR2/MISO1, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1. Applies to input pins: CLKIN, RESET, TRST.
3
ELECTRICAL CHARACTERISTICS
Parameter1 Description Test Conditions Min Typical Max Unit
VOH VOL IIH IIL IINP IILP IOZH IOZL IDD-IDLE1
High Level Output Voltage2 Low Level Output Voltage2 High Level Input Current3, 4 Low Level Input Current2 High Level Input Current5 Low Level Input Current3 Three-State Leakage Current6 Three-State Leakage Current5 Supply Current (Core) Idle1
@ VDDEXT = min, IOH = -0.5 mA @ VDDEXT = min, IOL = 2.0 mA @ VDDEXT = max, VIN = VDD max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = VDD max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = VDD max @ VDDEXT = max, VIN = 0 V PLL Enabled, CCLK = 160 MHz7
2.4 0.4 TBD TBD TBD TBD 10 10
V V A A A A A A mA
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Parameter1
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Typical Max Unit
ELECTRICAL CHARACTERISTICS
Description
(CONTINUED) Test Conditions Min
IDD-IDLE2
Supply Current (Core) Idle2
PLL Enabled, HCLK = 80 MHz, CCLK Disabled7 HCLK = 80 MHz, CCLK = 160 MHz7,8 HCLK = 80 MHz, CCLK = 160 MHz7,8 PLL Enabled, Core, HCLK Disabled7 HCLK = 80 MHz7 PLL, Core, HCLK, CLKIN Disabled7 fIN = 1 MHz, TCASE = 25C, VIN = 2.5 V
1
mA
IDD-TYPICAL
Supply Current (Core) Typical
184
mA
IDD-PEAK
Supply Current (Core) Peak
215
mA
IDD-PERIPHERAL1
Supply Current (Peripheral) Supply Current (Peripheral) Supply Current Input Capacitance9, 10
5 60 100 TBD
mA mA A pF
IDD-PERIPHERAL2 IDD-POWERDOWN
CIN
1 2
Specifications subject to change without notice. Applies to output and bidirectional pins: DATA15-0, ADDR21-0, HAD15-0, MS3-0, IOMS, RD, WR, CLKOUT, HACK, PF7-0, TMR2-0, BGH, BG, DT0, DT1, DT2/MISO0, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1, RFS2/MOSI1, BMS, TDO, TXD, EMU. Applies to input pins: ACK, BR, HCMS, HCIOMS, OPMODE, BMODE1-0, HA16, HALE, HRD, HWR, CLKIN, RESET, TCK, TDI, TMS, TRST, DR0, DR1, BYPASS, RXD. Applies to input pins with internal pull-ups: BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, RESET. Applies to input pin with internal pull-down: TRST Applies to three-statable pins: DATA15-0, ADDR21-0, MS3-0, RD, WR, PF7-0, BMS, IOMS, TFSx, RFSx, TDO, EMU. Test Conditions: @ VDDINT = 2.5V, TAMB = 25C Refer to Table 23 on page 52 for definitions of operation types. Applies to all signal pins. Guaranteed, but not tested.
3
4 5 6 7 8 9
10
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ABSOLUTE MAXIMUM RATINGS
VDDINTInternal (Core) Supply Voltage1,2 .......-0.3 to 3.0 V VDDEXTExternal (I/O) Supply Voltage ............-0.3 to 4.6 V VIL-VIHInput Voltage ......................-0.5 to VDDEXT +0.5 V VOL-VOHOutput Voltage Swing ........-0.5 to VDDEXT +0.5 V CLLoad Capacitance............................................ 200 pF tCCLKCore Clock Period........................................ 6.25 ns fCCLKCore Clock Frequency.............................. 160 MHz tHCLKPeripheral Clock Period...................................10 ns fHCLKPeripheral Clock Frequency...................... 100 MHz TSTOREStorage Temperature Range .............. -65 to 150C TLEADLead Temperature (5 seconds)...................... 185C
1 2
Specifications subject to change without notice. Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY
CAUTION: ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2196 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONS
This section contains timing information for the DSP's external signals.
24
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Clock In and Clock Out Cycle Timing
Table 8 and Figure 11 describe clock and reset operations. Per VDDINTInternal (Core) Supply Voltage, -0.3 to 3.0 V on page 24, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 160/100 MHz.
Table 8. Clock In and Clock Out Cycle Timing Parameter Description Min Max Unit
Switching Characteristic tCKOD tCKO CLKOUT delay from CLKIN CLKOUT period1 0 10 5.8 ns ns
Timing Requirements tCK tCKL tCKH tWRST tMSLS tMSLH
1
CLKIN period2,3 CLKIN low pulse CLKIN high pulse RESET asserted pulsewidth low MSELx/BYPASS stable before RESET asserted setup MSELx/BYPASS stable after RESET de-asserted hold
6.25 2.2 2.2 200tCLKOUT 160 1000
200
ns ns ns ns s ns
Figure 11 shows a 2 ratio between CLKOUT = 2 CLKIN (or tHCLK = 2 tCCLK), but the ratio has many programmable options. For more information see the System Design chapter of the ADSP-219x/2191 DSP Hardware Reference. In clock multiplier mode and MSEL6-0 set for 1:1 (or CLKIN=CCLK), tCK=tCCLK. In bypass mode, tCK=tCCLK.
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Programmable Flags Cycle Timing
Table 9 and Figure 12 describe programmable flag operations.
Table 9. Programmable Flags Cycle Timing Parameter Description Min Max Unit
Switching Characteristic tDFO tHFO Flag output delay with respect to HCLK Flag output hold after HCLK high TBD 3 TBD ns ns
Timing Requirement tHFI Flag input hold is asynchronous 3 ns
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Figure 12. Programmable Flags Cycle Timing
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Timer PWM_OUT Cycle Timing
Table 10 and Figure 13 describe timer expired operations. The input signal is asynchronous in "width capture mode" and has an absolute maximum input frequency of 50 MHz.
Table 10. Timer PWM_OUT Cycle Timing Parameter Description Min Max Unit
Switching Characteristic tHTO
1
Timer pulsewidth output1
6.25
(232-1) cycles
ns
The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232-1) cycles.
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Figure 13. Timer PWM_OUT Cycle Timing
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External Port Write Cycle Timing
Table 11 and Figure 14 describe external port write operations. The external port lets systems extend read/write accesses in three ways: waitstates, ACK input, and combined waitstates and ACK. To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP to wait, and the DSP requires two EMI clock cycles after ACK goes high to finish the access. For more information, see the External Port chapter in the ADSP-219x/2191 DSP Hardware Reference
Table 11. External Port Write Cycle Timing Parameter Description1, 2, 3 Min Max Unit
Switching Characteristics tCWA tCSWS tAWS tAKS tWSCS tWSA tCWD tWW tCDA tCDD tDSW tDHW tDHW EMI4 clock low to WR asserted delay Chip select asserted to WR de-asserted delay Address valid to WR setup and delay ACK asserted to EMI clock high delay WR de-asserted to chip select de-asserted WR de-asserted to address invalid EMI clock low to WR de-asserted delay WR strobe pulsewidth WR to data enable access delay WR to data disable access delay Data valid to WR de-asserted setup WR de-asserted to data invalid hold time; wt_hold=0 WR de-asserted to data invalid hold time; wt_hold=1 4.3 4.9 6.0 4.8 4.5 2.5 tHCLK -0.5 1.5 3.3 tHCLK -1.4 3.4 tHCLK +3.4 4.1 7.4 tHCLK +4.8 7.4 tHCLK +7.4 7.0 6.6 2.7 2.8 6.5 7.0 ns ns ns ns ns ns ns ns ns ns ns ns ns
Timing Requirement tAKW
1 2 3 4
ACK strobe pulsewidth
10.0
ns
tHCLK is the peripheral clock period. These are preliminary timing parameters that are based on worst-case operating conditions. The pad loads for these timing parameters are 20 pF. EMI clock is the external port clock that is generated from the EMI clock ratio. This signal is not available on an external pin, but (roughly) corresponds to HCLK (at similar clock ratios).
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External Port Read Cycle Timing
Table 12 and Figure 15 describe external port read operations. For additional information on the ACK signal, see the discussion on on page 28.
Table 12. External Port Read Cycle Timing Parameter Description1, 2, 3 Min Max Unit
Switching Characteristics tCRA tCSRS tARS tAKS tCRD tRSCS tRW tRSA EMI4 clock low to RD asserted delay Chip select asserted to RD asserted delay Address valid to RD setup and delay ACK asserted to EMI clock high delay EMI clock low to RD de-asserted delay RD de-asserted to chip select de-asserted setup RD strobe pulsewidth RD de-asserted to address invalid setup 4.3 4.9 6.0 2.5 4.8 tHCLK -0.5 4.5 6.6 2.7 7.0 2.8 6.5 7.0 ns ns ns ns ns ns ns ns
Timing Requirements tAKW tCDA tRDA tADA tSDA tSD tHRD
1 2 3 4
ACK strobe pulsewidth RD to data enable access delay RD asserted to data access setup Address valid to data access setup Chip select asserted to data access setup Data valid to RD de-asserted setup RD de-asserted to data invalid hold
10.0 0.0 tHCLK -5.5 tHCLK -0.2 tHCLK -0.6 1.8 0.0
ns ns ns ns ns ns ns
tHCLK is the peripheral clock period. These are preliminary timing parameters that are based on worst-case operating conditions. The pad loads for these timing parameters are 20 pF. EMI clock is the external port clock that is generated from the EMI clock ratio. This signal is not available on an external pin, but (roughly) corresponds to HCLK (at similar clock ratios).
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External Port Bus Request and Grant Cycle Timing
Table 13 and Figure 16 describe external port bus request and bus grant operations.
Table 13. External Port Bus Request and Grant Cycle Timing Parameter Description1, 2, 3 Min Max Unit
Switching Characteristics tSD tSE tDBG tEBG tDBH tEBH CLKOUT high to xMS, address, and RD/WR disable CLKOUT low to xMS, address, and RD/WR enable CLKOUT high to BG asserted setup CLKOUT high to BG de-asserted hold time CLKOUT high to BGH asserted setup CLKOUT high to BGH de-asserted hold time 4.3 4.0 2.2 2.2 2.4 2.4 ns ns ns ns ns ns
Timing Requirements tBS tBH
1 2 3
BR asserted to CLKOUT high setup CLKOUT high to BR de-asserted hold time
4.6 0.0
ns ns
tHCLK is the peripheral clock period. These are preliminary timing parameters that are based on worst-case operating conditions. The pad loads for these timing parameters are 20 pF.
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Host Port ALE Mode Write Cycle Timing
Table 14 and Figure 17 describe host port write operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.
Table 14. Host Port ALE Mode Write Cycle Timing Parameter Description Min Max Unit
Switching Characteristics tWHKS tWHKH tWHS tWHH HWR asserted to HACK asserted (setup, ACK Mode) HWR de-asserted to HACK de-asserted (hold, ACK Mode) HWR asserted to HACK asserted (setup, Ready Mode) HWR asserted to HACK de-asserted (hold, Ready Mode) 0.6 0.6+tNH1 2 0.6 2+tNH1 ns ns ns ns
Timing Requirements tCSAL tALPW tALCSW tWCSW tALW tWCS tHKWD tAALS tALAH tDWS tWDH
1
HCMS or HCIOMS asserted to HALE asserted HALE asserted pulsewidth HALE de-asserted to HCMS or HCIOMS de-asserted HWR de-asserted to HCMS or HCIOMS de-asserted HALE de-asserted to HWR asserted HWR de-asserted (after last byte) to HCMS or HCIOMS de-asserted (ready for next write) HACK asserted to HWR de-asserted (hold, ACK Mode) Address valid to HALE de-asserted (setup) HALE de-asserted to address invalid (hold) Data valid to HWR de-asserted (setup) HWR de-asserted to data invalid (hold)
0 4 1 1 1 1 1.5 4 1.5 4 1
ns ns ns ns ns ns ns ns ns ns ns
tNH are peripheral bus latencies (n t HCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time.
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Figure 17. Host Port ALE Mode Write Cycle Timing
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Host Port ACC Mode Write Cycle Timing
Table 15 and Figure 18 describe host port write operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.
Table 15. Host Port ACC Mode Write Cycle Timing Parameter Description Min Max Unit
Switching Characteristics tWHKS tWHKH tWHS tWHH HWR asserted to HACK asserted (setup, ACK Mode) HWR de-asserted to HACK de-asserted (hold, ACK Mode) HWR asserted to HACK asserted (setup, Ready Mode) HWR asserted to HACK de-asserted (hold, Ready Mode) 0.6 0.6+tNH1 2 0.6 2+tNH1 ns ns ns ns
Timing Requirements tWAL tCSAL tALCS tWCSW tALW tCSW tWCS tALEW tHKWD tADW tWAD tDWS tWDH
1
HWR asserted to HALE de-asserted (delay) HCMS or HCIOMS asserted to HALE asserted (delay) HALE de-asserted to optional HCMS or HCIOMS de-asserted HWR de-asserted to HCMS or HCIOMS de-asserted HALE asserted to HWR asserted HCMS or HCIOMS asserted to HWR asserted HWR de-asserted (after last byte) to HCMS or HCIOMS de-asserted (ready for next write) HALE de-asserted to HWR asserted HACK asserted to HWR de-asserted (hold, ACK Mode) Address valid to HWR asserted (setup) HWR de-asserted to address invalid (hold) Data valid to HWR de-asserted (setup) HWR de-asserted to data invalid (hold)
1.5 0 1 1 0.5 1 1 1 1.5 4 1 4 1 2
ns ns ns ns ns ns ns ns ns ns ns ns ns
tNH are peripheral bus latencies (n tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time.
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Figure 18. Host Port ACC Mode Write Cycle Timing
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Host Port ALE Mode Read Cycle Timing
Table 16 and Figure 19 describe host port read operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.
Table 16. Host Port ALE Mode Read Cycle Timing Parameter Description Min Max Unit
Switching Characteristics tRHKS tRHKH tRHS tRHH HRD asserted to HACK asserted (setup, ACK Mode) HRD de-asserted to HACK de-asserted (hold, ACK Mode) HRD asserted to HACK asserted (setup, Ready Mode) HRD asserted to HACK de-asserted (hold, Ready Mode) 2 2+tNH1 2 2 2+tNH1 ns ns ns ns
Timing Requirements tCSAL tALCS tRCSW tALR tRCS tALPW tHKRD tAALS tALAH tRDH
1
HCMS or HCIOMS asserted to HALE asserted (delay) HALE de-asserted to optional HCMS or HCIOMS de-asserted HRD de-asserted to HCMS or HCIOMS de-asserted HALE de-asserted to HRD asserted HRD de-asserted (after last byte) to HCMS or HCIOMS de-asserted (ready for next read) HALE asserted pulsewidth HACK asserted to HRD de-asserted (hold, ACK Mode) Address valid to HALE de-asserted (setup) HALE de-asserted to address invalid (hold) HRD de-asserted to data invalid (hold)
0 1 1 1 1 4 1.5 4 1 1
ns ns ns ns ns ns ns ns ns ns
tNH are peripheral bus latencies (n tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time.
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Figure 19. Host Port ALE Mode Read Cycle TIming
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Host Port ACC Mode Read Cycle Timing
Table 17 and Figure 20 describe host port read operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.
Table 17. Host Port ACC Mode Read Cycle Timing Parameter Description Min Max Unit
Switching Characteristics tRHKS tRHKH tRHS tRHH HRD asserted to HACK asserted (setup, ACK Mode) HRD de-asserted to HACK de-asserted (hold, ACK Mode) HRD asserted to HACK asserted (setup, Ready Mode) HRD asserted to HACK de-asserted (hold, Ready Mode) 1 1+tNH1 2 1 2+tNH1 ns ns ns ns
Timing Requirements tCSAL tALCS tRCSW tALW tALER tCSR tRCS tWAL tHKRD tADW tWAD tRDH
1
HCMS or HCIOMS asserted to HALE asserted (delay) HALE de-asserted to optional HCMS or HCIOMS de-asserted HRD de-asserted to HCMS or HCIOMS de-asserted HALE asserted to HWR asserted HALE de-asserted to HWR asserted HCMS or HCIOMS asserted to HRD asserted HRD de-asserted (after last byte) to HCMS or HCIOMS de-asserted (ready for next read) HWR de-asserted to HALE de-asserted (delay) HACK asserted to HRD de-asserted (hold, ACK Mode) Address valid to HWR de-asserted (setup) HWR de-asserted to address invalid (hold) HRD de-asserted to data invalid (hold)
0 1 1 0.5 1 1 1 1.5 1.5 4 1 1 2
ns ns ns ns ns ns ns ns ns ns ns ns
tNH are peripheral bus latencies (n tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time.
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Figure 20. Host Port ACC Mode Read Cycle TIming
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Serial Port (SPORT) Clocks and Data Timing
Table 18 and Figure 21 describe SPORT transmit and receive operations.
Table 18. Serial Port (SPORT) Clocks and Data Timing1 Parameter Description Min Max Unit
Switching Characteristics tHOFSE tDFSE tDDTEN tDDTTE tDDTIN tDDTTI RFS Hold after RCLK (Internally Generated RFS)2 RFS Delay after RCLK (Internally Generated RFS)2 Transmit Data Delay after TCLK2 Data Disable from External TCLK2 Data Enable from Internal TCLK2 Data Disable from Internal TCLK2 0 0 0 0 0 0 12.4 12.4 12.1 12.0 6.8 6.3 ns ns ns ns ns ns
Timing Requirements tSCLKIW tSFSI tHFSI tSDRI tHDRI tSCLKW tSFSE tHFSE tSDRE tHDRE
1
TCLK/RCLK Width TFS/RFS Setup before TCLK/RCLK3 TFS/RFS Hold after TCLK/RCLK3, 4 Receive Data Setup before RCLK3 Receive Data Hold after RCLK3 TCLK/RCLK Width TFS/RFS Setup before TCLK/RCLK3 TFS/RFS Hold after TCLK/RCLK3, 4 Receive Data Setup before RCLK3 Receive Data Hold after RCLK3
20 -0.6 -0.3 -2.3 1.9 20 -0.6 -0.6 -2.2 1.8
ns ns ns ns ns ns ns ns ns ns
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Referenced to drive edge. Referenced to sample edge. RFS hold after RCLK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCLK for late external TFS is 0 ns minimum from drive edge.
2 3 4
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Serial Port (SPORT) Frame Synch Timing
Table 19 and Figure 22 describe SPORT frame synch operations. To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) R/TCLK width.
Table 19. Serial Port (SPORT) Frame Synch Timing Parameter Description Min Max Unit
Switching Characteristics tHOFSE tHOFSI tDDTENFS tDDTLFSE tHDTE tHDTI tDDTE tDDTI RFS Hold after RCLK (Internally Generated RFS)1 TFS Hold after TCLK (Internally Generated TFS)1 Data Enable from late FS or MCE = 1, MFD = 02 Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 03 Transmit Data Hold after TCLK (external clk)1 Transmit Data Hold after TCLK (internal clk)1 Transmit Data Delay after TCLK (external clk)1 Transmit Data Delay after TCLK (internal clk)1 0 0 0 12.4 12.2 4.7 4.7 12.4 12.2 12.2 11.1 ns ns ns ns ns ns ns ns
Timing Requirements tSFSE tSFSI
1 2 3
TFS/RFS Setup before TCLK/RCLK (external clk)3 TFS/RFS Setup before TCLK/RCLK (internal clk)3
-0.6 -0.6
TBD TBD
ns ns
Referenced to drive edge. MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS. Referenced to sample edge.
44
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Serial Peripheral Interface (SPI) Port--Master Timing
Table 20 and Figure 23 describe SPI port master operations.
Table 20. Serial Peripheral Interface (SPI) Port--Master Timing Parameter Description Min Max Unit
Switching Characteristics tSDSCIM tSPICHM tSPICLM tSPICLK tHDSM tSPITDM tDDSPID tHDSPID SPIxSEL low to first SCLK edge (x=0 or 1) Serial clock high period Serial clock low period Serial clock period Last SCLK edge to SPIxSEL high (x=0 or 1) Sequential transfer delay SCLK edge to data out valid (data out delay) SCLK edge to data out invalid (data out hold) 2tHCLK 2tHCLK 2tHCLK 4tHCLK 2tHCLK 2tHCLK 0 0 6 5 ns ns ns ns ns ns ns ns
Timing Requirements tSSPID tHSPID Data input valid to SCLK edge (data input setup) SCLK sampling edge to data input invalid 1.6 1.6 ns ns
46
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Serial Peripheral Interface (SPI) Port--Slave Timing
Table 21 and Figure 24 describe SPI port slave operations.
Table 21. Serial Peripheral Interface (SPI) Port--Slave Timing Parameter Description Min Max Unit
Switching Characteristics tDSOE tDSDHI tDDSPID tHDSPID SPISS assertion to data out active SPISS deassertion to data high impedance SCLK edge to data out valid (data out delay) SCLK edge to data out invalid (data out hold) 0 0 0 0 6 6 5 5 ns ns ns ns
Timing Requirements tSPICHS tSPICLS tSPICLK tHDS tSPITDS tSDSCI tSSPID tHSPID Serial clock high period Serial clock low period Serial clock period Last SPICLK edge to SPISS not asserted Sequential Transfer Delay SPISS assertion to first SPICLK edge Data input valid to SCLK edge (data input setup) SCLK sampling edge to data input invalid 2tHCLK 2tHCLK 4tHCLK 2tHCLK 2tHCLK 2tHCLK 1.6 1.6 ns ns ns ns ns ns ns ns
48
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Universal Asynchronous Receiver-Transmitter (UART) Port--Receive and Transmit Timing
Figure 25 describes UART port receive and transmit operations. The maximum baud rate is HCLK/16. As shown in Figure 25 there is some latency between the generation
internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.
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50
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JTAG Test And Emulation Port Timing
Table 22 and Figure 26 describe JTAG port operations.
Table 22. JTAG Port Timing Parameter Description Min Max Unit
Switching Characteristics tDTDO tDSYS TDO Delay from TCK Low System Outputs Delay After TCK Low1 0 4 5 ns ns
Timing Parameters tTCK tSTAP tHTAP tSSYS tHSYS tTRSTW
1
TCK Period TDI, TMS Setup Before TCK High TDI, TMS Hold After TCK High System Inputs Setup Before TCK Low2 System Inputs Hold After TCK Low2 TRST Pulsewidth3
20 4 4 4 5 4
ns ns ns ns ns ns
System Outputs = DATA15-0, ADDR21-0, MS3-0, RD, WR, ACK, CLKOUT, BG, PF7-0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS. System Inputs = DATA15-0, ADDR21-0, RD, WR, ACK, BR, BG, PF7-0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, CLKIN, RESET. 50 MHz max.
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Output Drive Currents
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Figure 27 shows typical I-V characteristics for the output drivers of the ADSP-2196. The curves represent the current drive capability of the output drivers as a function of output voltage.
Power Dissipation
Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Using the current-versus-operation information in Table 23, designers can estimate the ADSP-2196's internal power supply (VDDINT) input current for a specific application, according to the formula in Figure 28.
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Figure 27. ADSP-2196 Typical Drive Currents Table 23. ADSP-2196 Operation Types Versus Input Current IDD(mA)1 CCLK = 80 MHz Core Peripheral Core IDD (mA)1 CCLK = 160 MHz Peripheral
Activity
Power down2 Idle 13 Idle 24 Typical5 Peak6
1 2 3 4
0 0 0 95 112
0 3 30 30 30
0 0 0 184 215
0 5 60 60 60
Test conditions: VDD= 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; TAMB = 25 C. PLL, Core, peripheral clocks, and CLKIN are disabled. PLL is enabled and Core and peripheral clocks are disabled. Core CLK is disabled and peripheral clock is enabled. This is a power- down interrupt mode. The timer can be used to generate an interrupt to enable the Core clock. All instructions execute from internal memory. 100% of the instructions are MAC with dual operand addressing, with changing data fetched using a linear address sequence, and 50% of the instructions move data from PM to a data register. All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using a linear address sequence.
5
6
IDDINT = ( %Peak x I DD-PEAK ) + %Typical x I DD-TYPICAL ) + ( %Idle x I DD-IDLE ) + ( %Powerdown x I DD-PWRDWN )
Figure 28. IDDINT Calculation
The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: * The number of output pins that switch during each cycle (O) * The maximum frequency at which they can switch (f) 52
* Their load capacitance (C) * Their voltage swing (VDD) and is calculated by the formula in Figure 29.
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P EXT = O x C x V DD x f Figure 29. PEXT Calculation
2
The load capacitance should include the processor's package capacitance (CIN). The switching frequency includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2tCK). The write strobe can switch every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but selects can switch on each cycle. For example, estimate PEXT with the following assumptions: * A system with one bank of external data memory--asynchronous RAM (16-bit) * One 64K 16 RAM chip is used, each with a load of 10 pF * Maximum peripheral speed HCLK = 100 MHz * External data memory writes occur every other cycle, a rate of 1/(4tHCLK), with 50% of the pins switching * The bus cycle time is 100 MHz (tHCLK = 20 nsec)
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The PEXT equation is calculated for each class of pins that can drive as shown in Table 24.
Table 24. PEXT Calculation Pin Type # of Pins % Switching C f VDD2 = PEXT
Address MSx WR Data CLKOUT
15 1 1 16 1
50 0 -- 50 --
TBD pF TBD pF TBD pF TBD pF TBD pF
25.0 MHz 25.0 MHz 25 MHz 25.0 MHz 100 MHz
10.9 V 10.9 V 10.9 V 10.9 V 10.9 V
=TBD W =TBD W =TBD W =TBD W =TBD W PEXT =TBD W
A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation with the formula in Figure 30.
P TOTAL = P EXT + P INT Figure 30. PTOTAL (Typical) Calculation
The output disable time tDIS is the difference between tMEASURED and tDECAY as shown in Figure 32. The time tMEASURED is the interval from when the reference signal switches to when the output voltage decays -V from the measured output high or output low voltage. The tDECAY is calculated with test loads CL and IL, and with -V equal to 0.5 V.
Where: * PEXT is from Table 24 * PINT is IDDINT 2.5V, using the calculation IDDINT listed in Power Dissipation on page 52 Note that the conditions causing a worst-case PEXT are different from those causing a worst-case PINT. Maximum PINT cannot occur while 100% of the output pins are switching from all ones to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously.
Test Conditions
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The DSP is tested for output enable, disable, and hold time.
Output Disable Time
Figure 32. Output Enable/Disable Output Enable Time
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by - V is dependent on the capacitive load, CL and the load current, IL. This decay time can be approximated by the equation in Figure 31.
C L V tDECAY = --------------IL Figure 31. Decay Time Calculation
Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The output enable time tENA is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram (Figure 32). If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
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rise time varies with capacitance. These figures also show graphically how output delays and holds vary with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on page 54.) The graphs in these figures may not be linear outside the ranges shown.
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0.4 V. CL is the total bus capacitance (per data line), ,13 8 7 25 9 and IL 9the total leakage or is 2 87 3 87 three-state current (per data line). The hold time will be Figure 34. Voltage Reference Levels AC t for DECAY plus the minimum Measurements Enable/Disable) disable time (i.e., t Output (Except 9 DATRWH for the write cycle).
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Example System Hold Time Calculation
Capacitive Loading
Figure 33. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
To determine the data output hold time in a particular ,2 + system, first calculate tDECAY using the equation given in Figure 31. Choose -V to be the difference between the ADSP-2196's output voltage and the input threshold for the device requiring the hold time. A typical -V will be
Output delays and holds are based on standard capacitive loads: 50 pF on all pins (see Figure 37). The delay and hold specifications given should be derated by a factor of 1.5 ns/50 pF for loads other than the nominal value of 50 pF. Figure 35 and Figure 36 show how output

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Figure 35. Typical Output Rise Time (10%-90%, VDDEXT =Max) vs. Load Capacitance Environmental Conditions
The thermal characteristics in which the DSP is operating influence performance.
Thermal Characteristics
be used. A heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive.
* CA = Value from Table 25. * JB = TBDC/W There are some important things to note about these TAMB calculations and the values in Table 25: * This represents thermal resistance at total power of TBD W. * For the LQFP package: JC = 0.96C/W For the mini-BGA package: JC = 8.4C/W
The ADSP-2196 comes in a Where: 144-lead LQFP or 144-lead * TAMB = Ambient temperaBall Grid Array (mini-BGA) ture (measured near top package. The ADSP-2196 is surface of package) specified for an ambient tem- * PD = Power dissipation in perature (TAMB) as calculated W (this value depends using the formula in upon the specific applicaFigure 38. To ensure that the tion; a method for TAMB data sheet specification calculating PD is shown is not exceeded, a heatsink under Power Dissipation). and/or an air flow source may REV. PrA
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Figure 36. Typical Output Rise Time (10%-90%, VDDEXT =Min) vs. Load Capacitance
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Figure 37. Typical Output Delay or Hold vs. Load Capacitance (at Max Case Temperature)
T AMB = T CASE - PD x CA
Figure 38. TCASE Calculation Table 25. CA Values1
Airflow (Linear Ft./Min.) Airflow (Meters/Second) LQFP: CA (C/W) Mini-BGA:
CA (C/W)
0 0 44.3 26
100 0.5 41.4 24
200 1 38.5 22
400 2 35.3 20.9
600 3 32.1 19.8
56
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1
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These are preliminary estimates.
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ADSP-2196 144-Lead LQFP Pinout
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Table 26. 144-Lead LQFP Pins (Alphabetically By Signal) (Continued) SIGNAL PIN #
Table 26. 144-Lead LQFP Pins (Alphabetically By Signal) (Continued) SIGNAL PIN #
Table 26. 144-Lead LQFP Pins (Alphabetically By Signal) (Continued) SIGNAL PIN #
Table 26 lists the LQFP pinout by signal name.
Table 26. 144-Lead LQFP Pins (Alphabetically By Signal) SIGNAL PIN #
BMODE1 BMS BR BYPASS CLKOUT D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DR0 DR1 DR2 DT0 DT1 DT2 EMU HACK HACK_P
71 113 112 72 130 123 124 125 126 128 135 136 137 138 139 140 141 142 144 1 2 60 67 49 56 64 46 81 26 24
HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAD8 HAD9 HAD10 HAD11 HAD12 HAD13 HAD14 HAD15 HA16 HALE HCMS HCIOMS HRD HWR IOMS MS0 MS1 MS2 MS3 OPMODE CLKIN XTAL
3 4 6 7 8 9 10 11 12 14 15 17 18 20 21 22 23 30 27 28 31 32 114 115 116 117 119 83 132 133
PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 RCLK0 RCLK1 RCLK2 RESET RFS0 RFS1 RFS2 RD RXD TCK TCLK0 TCLK1 TCLK2 TDI TDO TFS0 TFS1 TFS2 TMR0 TMR1 TMR2 TMS
34 35 36 37 38 39 41 42 61 68 50 73 62 69 51 122 52 78 57 65 47 75 74 59 66 48 43 44 45 76 REV. PrA
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 ACK BG BGH BMODE0
84 85 86 87 88 89 91 92 93 95 96 97 98 99 101 102 103 104 106 107 108 109 120 111 110 70
58
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Table 26. 144-Lead LQFP Pins (Alphabetically By Signal) (Continued) SIGNAL PIN #
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Table 27. 144-Lead LQFP Pins (Numerically By Pin Number (Continued) SIGNAL PIN #
Table 27 lists the LQFP pinout by pin number.
Table 27. 144-Lead LQFP Pins (Numerically By Pin Number SIGNAL PIN #
Table 27. 144-Lead LQFP Pins (Numerically By Pin Number (Continued) SIGNAL PIN #
TRST TXD VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT GND GND GND GND GND GND GND GND GND GND GND GND WR
79 53 13 25 40 63 90 100 118 131 143 19 58 82 127 5 16 29 33 54 55 77 80 94 105 129 134 121 D14 D15 HAD0 HAD1 GND HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAD8 VDDEXT HAD9 HAD10 GND HAD11 HAD12 VDDINT HAD13 HAD14 HAD15 HA16 HACK_P VDDEXT HACK HCMS HCIOMS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
GND HALE HRD HWR GND PF0 PF1 PF2 PF3 PF4 PF5 VDDEXT PF6 PF7 TMR0 TMR1 TMR2 DT2 TCLK2 TFS2 DR2 RCLK2 RFS2 RXD TXD GND GND DT0 TCLK0 VDDINT
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
TFS0 DR0 RCLK0 RFS0 VDDEXT DT1 TCLK1 TFS1 DR1 RCLK1 RFS1 BMODE0 BMODE1 BYPASS RESET TDO TDI TMS GND TCK TRST GND EMU VDDINT OPMODE A0 A1 A2 A3 A4
59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 REV. PrA
59
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Table 27. 144-Lead LQFP Pins (Numerically By Pin Number (Continued) SIGNAL PIN #
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A5 VDDEXT A6 A7 A8 GND A9 A10 A11 A12 A13 VDDEXT A14 A15 A16 A17 GND A18 A19 A20 A21 BGH BG BR BMS IOMS MS0 MS1 MS2 VDDEXT 60
89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118
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Table 27. 144-Lead LQFP Pins (Numerically By Pin Number (Continued) SIGNAL PIN #
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ADSP-2196
MS3 ACK WR RD D0 D1 D2 D3 VDDINT D4 GND CLKOUT VDDEXT CLKIN XTAL GND D5 D6 D7 D8 D9 D10 D11 D12 VDDEXT D13
119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
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ADSP-2196 144-Lead Mini-BGA Pinout
Table 28 lists the mini-BGA pinout by signal name.
Table 28. 144-Lead Mini-BGA Pins (Alphabetically By Signal)
Table 28. 144-Lead Mini-BGA Pins (Alphabetically By Signal) (Continued) SIGNAL BALL #
BMS
SIGNAL BALL #
A10 B9 M11 A5 C6 D7 A7 C7 A6 B7 A4 C5 B5 D5 A3 C4 B4 C3 A2 B1 B2 L7 K9 L5 J6 L8 H4 J10 H3 G1 62
BR BYPASS CLKIN CLKOUT D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DR0 DR1 DR2 TCLK0 DT1 DT2 EMU HACK HACK_P
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 ACK BG BGH BMODE0 BMODE1
J11 H9 H10 G12 H11 G10 F12 G11 F10 F11 E12 E11 E10 E9 D11 D10 D12 C11 C12 B12 B11 A11 A8 C10 B10 L10 L9
REV. PrA
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35(/,0,1$5< 7(&+1,&$/ '$7$ September 2001
For current information contact Analog Devices at 800/262-5643
ADSP-2196
Table 28. 144-Lead Mini-BGA Pins (Alphabetically By Signal) (Continued) SIGNAL BALL #
Table 28. 144-Lead Mini-BGA Pins (Alphabetically By Signal) (Continued) SIGNAL BALL #
HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAD8 HAD9 HAD10 HAD11 HAD12 HAD14 HAD15 HAD13 HA16 HALE HCIOMS HCMS HRD HWR IOMS MS0 MS1 MS2 MS3 OPMODE PF0 PF1 REV. PrA
C1 B3 C2 D1 D4 D3 D2 E1 E4 E2 F1 E3 F2 F3 G3 G2 H2 J1 J3 H1 J2 K2 E8 D9 A9 C9 D8 H12 K1 L1
PF2 PF3 PF4 PF5 PF6 PF7 RCLK0 RCLK1 RCLK2 RD RESET RFS0 RFS1 RFS2 RXD TCK DT0 TCLK1 TCLK2 TDI TDO TFS0 TFS1 TFS2 TMR0 TMR1 TMR2 TMS TRST TXD
M2 L2 M3 L3 K3 M4 K7 J9 J5 B8 L12 K8 M10 M6 K6 K11 H6 M9 K5 K12 L11 M8 J8 M5 K4 L4 J4 K10 J12 M7 63
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
35(/,0,1$5< 7(&+1,&$/ '$7$ September 2001
For current information contact Analog Devices at 800/262-5643
ADSP-2196
Table 28. 144-Lead Mini-BGA Pins (Alphabetically By Signal) (Continued) SIGNAL BALL #
Table 29 lists the mini-BGA pinout by ball number.
Table 29. 144-Lead Mini-BGA Pins (Numerically By Ball Number) SIGNAL BALL #
VDDINT VDDINT VDDINT VDDINT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT GND GND GND GND GND GND GND GND GND GND GND GND GND WR XTAL
D6 GND F4 D13 G9 D9 J7 D5 E5 CLKIN E6 D3 F5 D1 F6 ACK G7 MS1 G8 BMS H7 A21 H8 GND A1 D14 A12 D15 E7 HAD1 F7 D11 F8 D7 F9 XTAL G4 D4 G5 RD G6 BR H5 BGH L6 A20 M1 A19 M12 HAD0 C8 HAD2 B6 D12 D10 D6 C3 C4 C5 C2 C1 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
REV. PrA
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64
35(/,0,1$5< 7(&+1,&$/ '$7$ September 2001
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ADSP-2196
Table 29. 144-Lead Mini-BGA Pins (Numerically By Ball Number) (Continued) SIGNAL BALL #
Table 29. 144-Lead Mini-BGA Pins (Numerically By Ball Number) (Continued) SIGNAL BALL #
CLKOUT D2 WR MS2 BG A17 A18 HAD3 HAD6 HAD5 HAD4 D8 VDDINT D0 MS3 MS0 A15 A14 A16 HAD7 HAD9 HAD11 HAD8 VDDEXT VDDEXT GND IOMS A13 A12 A11
C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11
A10 HAD10 HAD12 HAD14 VDDINT VDDEXT VDDEXT GND GND GND A8 A9 A6 HACK_P HAD13 HAD15 GND GND GND VDDEXT VDDEXT VDDINT A5 A7 A3 HCMS HA16 HACK DT2 GND
E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5
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65
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ADSP-2196
Table 29. 144-Lead Mini-BGA Pins (Numerically By Ball Number) (Continued) SIGNAL BALL #
Table 29. 144-Lead Mini-BGA Pins (Numerically By Ball Number) (Continued) SIGNAL BALL #
DT0 VDDEXT VDDEXT A1 A2 A4 OPMODE HALE HRD HCIOMS TMR2 RCLK2 TCLK0 VDDINT TFS1 RCLK1 EMU A0 TRST PF0 HWR PF6 TMR0 TCLK2 RXD RCLK0 RFS0 DR1 TMS TCK
H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11
TDI PF1 PF3 PF5 TMR1 DR2 GND DR0 DT1 BMODE1 BMODE0 TDO RESET GND PF2 PF4 PF7 TFS2 RFS2 TXD TFS0 TCLK1 RFS1 BYPASS GND
K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
REV. PrA
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66
35(/,0,1$5< 7(&+1,&$/ '$7$ September 2001
.
144-LEAD METRIC THIN PLASTIC QUAD FLATPACK (LQFP) (ST-144)
0 $; 6 ( $7 ,1* 3 / $1(

For current information contact Analog Devices at 800/262-5643
ADSP-2196
OUTLINE DIMENSIONS
%6 & 64 %6 & 64

7 2 3 9 ,( :
3,16 ' 2 : 1
7 < 3
0 $; 12 7 ( 6

%6 & / ( $' 3,7 & +
',0 ( 16 ,2 16 ,1 0 ,/ / ,0 ( 7( 5 6 $& 7 8$/ 3 2 6 ,7,2 1 2 ) ( $& + / ( $' ,6 : ,7 +,1 2 ) ,7 6 ,' ($ / 32 6 ,7 ,2 1 : + ( 1 0 ( $6 85 ( ' ,1 7+ ( / $7 ( 5$/ ' ,5( &7 ,2 1 &( 1 7( 5 ',0 ( 16 ,2 16 $ 5( 12 0 ,1$ /
144-BALL MINI-BGA (CA-144)
64 $ & 2 5 1 ( 5 ,1 '( ; 75 ,$1 * /( $ % & ' ( ) * + . / 0 %2 7 7 2 0 9 ,( : '( 7 $ ,/ $ 0 $; 12 7 ( 6 ',0 ( 1 6 ,2 16 ,1 0 ,/ /,0 ( 7 ( 56 $& 7 8$ / 32 6 ,7 ,2 1 2 ) 7+ ( %$ / / * 5,' ,6 : ,7+ ,1 2 ) ,76 ,'( $/ 3 2 6 ,7 ,2 1 5 ( /$ 7 ,9 ( 72 7 +( 3 $ &. $* ( ( '* ( 6 $& 7 8$ / 32 6 ,7 ,2 1 2 ) ($ &+ %$ / / ,6 : ,7 +,1 2 ) ,76 ,' ($/ 3 2 6 ,7 ,2 1 5( / $ 7,9( 7 2 7 + ( %$ // * 5,' &( 1 7 ( 5 ',0 ( 1 6 ,2 1 6 $5 ( 12 0 ,1$ / %$ / / ',$0 ( 7( 5 '( 7 $ ,/ $ 0 $; 6 ( $7 ,1 * 3 / $1 (
%6 & 64 %6 & %$ / / 3 ,7 &+
7 2 3 9 ,( :
REV. PrA
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67
35(/,0,1$5< 7(&+1,&$/ '$7$ September 2001
Part Number1, 2
For current information contact Analog Devices at 800/262-5643
ADSP-2196
Operating Voltage
ORDERING GUIDE Ambient Temperature Range Instruction Rate On-Chip SRAM
ADSP-2196MKST -160X 0C to 70C ADSP-2196MBST -140X -40C to 85C
160 MHz 140 MHz 160 MHz 140 MHz
1.3M bit 1.3M bit 1.3M bit 1.3M bit
2.5 Int./3.3 Ext. V 2.5 Int./3.3 Ext. V 2.5 Int./3.3 Ext. V 2.5 Int./3.3 Ext. V
ADSP-2196MKCA-160X 0C to 70C ADSP-2196MBCA-140X -40C to 85C
1 2
ST = Plastic Thin Quad Flatpack (LQFP). CA = Chip array package
REV. PrA
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